1. Field of the Invention
The present invention relates to growth of semiconductor materials and devices, and, more particularly, to heteroepitaxial growth such as gallium arsenide on silicon and devices in such heterostructures.
2. Description of the Related Art
The growth of high quality gallium arsenide (GaAs) or other III-V compound semiconductors on silicon substrates is recognized as a desirable goal for the fabrication of advanced semiconductor devices. Specific advantages of this combination of materials include the availability of GaAs with high electron mobility and optical activity on a silicon substrate with improved mechanical strength and thermal conductivity over that obtainable with GaAs substrates. In addition, the growth of high quality GaAs on silicon offers the possibility of monolithically integrating GaAs and silicon devices for advanced electronic components. A number of workers have previously described advanced GaAs devices fabricated on silicon substrates as well as the successful cointegration of silicon and GaAs devices.
One of the key limitations in the implementation of device structures based on heteroepitaxial GaAs on silicon has been the 4.1% difference in lattice parameters between the two materials. This lattice mismatch leads to the formation of a network of misfit dislocations at the heterointerface; under typical epitaxial growth conditions, a significant fraction of these misfit defects thread away from the interface and into the GaAs regions where devices are subsequently fabricated. It is the presence of these threading dislocations (which can serve as recombination and scattering centers) that has seriously limited the implementation of GaAs on silicon technology.
A number of schemes have been reported for either annihiliating or retarding the propagation of threading dislocations in lattice mismatched semiconductors such as GaAs on silicon. Notably among these is post-growth thermal annealing for defect reduction; see J. W. Lee et al, 50 Appl. Phys. Lett. 31 (1987), Choi et al, 50 Appl. Phys. Lett. 992 (1987). Post-growth annealing by itself has been shown to be effective at reducing the global defect in GaAs layers on silicon substrates; however, there is insufficient data at this time to determine its effectivenes at lowering the density of device degrading threading dislocations. Similarly, Fan et al., U.S. Pat. No. 4,632,712, interrupts the GaAs growth to trap threading dislocations. Alternatively, a number of workers have studied the use of either compositional or thermally cycled superlattices during the growth process for dislocation control; see J. W. Lee, Proc. 1986 Int'l. Symp. on GaAs and Related Compounds 111 (1987), T. Soga et al, 26 Japan. J. Appl. Phys. L536 (1987), R. D. Dupuis et al, 50 Appl. Phys. Lett. 407 (1987). It appears from this literature that the primary effect of an intermediary superlattice is to deflect the threading dislocations by the imposition of a strain field (either by thermal effects in the case of the thermally cycled layer or by lattice dilations in the case of chemical superlattices) in such a way that they tend to propagate parallel instead of obliquely to the heterointerface. See Szilagyi et al, 4 J. Vac. Sci. Tech. A 2200 (1986). FIG. 1 illustrates in schematic cross sectional elevation view a threading dislocation that originates at point A at the heterointerface and propagates to point B in the superlattice, follows the superlattice to point C, and then continues propagation through the GaAs to surface point D. If the dislocation is annihilated in the superlattice or if it propagates long distances in the superlattice (distance from point B to point C), then the dislocation is effectively kept away from devices formed at the surface. However, a significant fraction of dislocations appear to propagate no more than about 10 to 20 .mu.m in the superlattice and eventually reach the surface.
Recent work has demonstrated that it is possible to selectively grow islands of GaAs epitaxially onto silicon substrates when the latter is patterned with a mask of material such as silicon dioxide or silicon nitride; the silicon is exposed through openings about 1 mm square. See Matyi et al, 51 Appl. Phys. Lett. 637 (1987), Matyi et al, 6 J.Vac.Sci.Tech.B 699 (1988). The effect of post-growth annealing on the patterned epitaxial layer has been found to be dramatic; in addition to lowering the overall defect density, post growth annealing also has been observed to drive a solid state recrystallization of the polycrystalline GaAs that was originally grown on top of the patterning mask to extend the single crystal islands about 1 to 2 .mu.m.
Also, growth of GaAs on silicon mesas has been demonstrated with smaller mesas yielding lower defect densities; see E. Fitzgerlad et al, 52 Appl.Phys.Lett. 1496 (1988).
However, the known methods still have unacceptably high threading dislocation densities for GaAs epitaxially grown on silicon.